The present invention relates to drive circuits and, more specifically, to drive circuits with over-voltage protection that provide a voltage greater than a supply voltage. Such circuits are beneficial for pixel cells as discussed herein and for other uses where a greater than VDD (or VCC) voltage is desired.
Photosensitive or xe2x80x9cpixelxe2x80x9d cells and drive circuits for powering those cells are known in the art. A typical drive circuit consists of a conventional buffer that is capable of propagating to a pixel cell or other circuit a voltage level that is no higher than a logic high voltage level. In CMOS circuits this voltage high level is often VDD. As discussed in more detail below, this limitation is disadvantageous in use with pixel cells and other types of circuits.
Referring to FIG. 1, a representative photosensitive cell 10 is shown. Cell 10 includes three transistors 12-14 (which are typically n-type field-effect transistors) and a light sensitive or xe2x80x9cphotoxe2x80x9d diode 15. Transistors 12 and 13 are coupled to VDD and transistor 14 is coupled to the source of transistor 13. A row reset signal is applied to the gate of transistor 12 and a row select signal is applied to the gate of transistor 14.
In a typical mode of operation, the row reset line is asserted high to charge the parasitic capacitance of the reversed biased photo diode to a reset level. After diode output node 17 has stabilized, the row reset is pulled low, allowing photo induced charge carriers to discharge the photo diode at a rate proportional to the incident light intensity. After a specific exposure time, the row select line is asserted high allowing the voltage at node 17 to be sampled at the cell output node 19 (normally coupled to a column of pixel cell outputs), through source follower buffer transistor 13. The row reset signal is again asserted high and low to reset node 17 a second time. The reset level is sampled at output 19. The difference between the voltage level at output 19 after exposure to incident light and at a reset level is proportional to the incident light intensity.
The row reset signal is driven by a digital gate that limits the high level of row reset to VDD as this is typically the highest available supply voltage on a CMOS integrated circuit. While beneficial for some purposes, the use in a typical pixel cell of a row reset signal with a high level limited to VDD has disadvantageous aspects.
One disadvantageous aspect is that the dynamic range at output 18 is limited to a maximum of VDDxe2x88x92(2xc3x97 the NMOS threshold, Vtn). One Vtn is lost at transistor 12 and the other is lost at transistor 13. Thus, dynamic range for a 3.3V VDD cell is approximately 3.3xe2x88x92(2xc3x970.8) or 1.7 to 0.4 (the turn-off voltage of a current source transistor coupled to pixel column output 19). This results in a typical dynamic range magnitude of 1.3V.
Another disadvantageous aspect is that the row reset signal must be held high for a relatively long time, on the order of 100 microseconds, before node 17 reaches its final settled voltage due to sub-threshold leakage currents at transistor 12 as that transistor approaches its cutoff state. Due to timing constraints, imaging systems may be forced to use a shorter reset interval. Shorter reset intervals can in turn result in a difference between the xe2x80x9cbefore exposurexe2x80x9d reset and the xe2x80x9cafter exposurexe2x80x9d reset signal strengths. The net effect is a memory of the previous captured image which can either add to or subtract from the present captured image, giving the appearance of a positive or negative ghost image superimposed on the desired image.
Accordingly, it is an object of the present invention to provide a drive circuit that is capable of improving performance in a pixel cell or other circuit. It is another object of the present invention to provide a drive circuit that is capable of producing an output signal that is greater than a supply voltage and that provides suitable over-voltage protection.
Is also an object of the present invention to provide a drive circuit that increases dynamic range and that increases the rate at which stable states and reset levels are reached in a pixel cell.
These and related objects of the present invention are achieved by use of a drive circuit with over voltage protection for use with pixel cells and other circuits as described herein.
The use of such a drive circuit with a pixel cell permits the delivery of a higher voltage level reset signal to the row reset transistor of that cell. A first advantage of a higher row reset signal or gate voltage is that it allows the photo diode cathode (node 17) to be reset all the way to VDD without altering the pixel design, thus increasing the dynamic range of the cell by Vtn. This can be a dynamic range improvement approaching a factor of 2, depending on supply voltage level and process specifics like threshold dependence on back bias.
A second advantage is that since the cell reset transistor never approaches cutoff during reset, the diode output node charges to the reset level much faster. A third advantage is that because node 17 resets all the away to VDD, the final reset level is not dependent upon the discharge level of the photo diode prior to the reset operation, thereby eliminating the occurrence of ghost images.
An additional advantage is that the higher reset level results in a stronger reverse bias on the photo diode, resulting in smaller parasitic depletion capacitance. The smaller capacitance results in higher sensitivity to photo generated charge carriers and potentially improves image quality in low lighting conditions.
In addition to use with pixel cells, the drive circuit of the present invention may be used in any application where the designer desires to use a non-complementary transmission gate for gating signals with large dynamic range. For example, the gate of an n-channel MOS device can be driven by a similar drive circuit to allow it to control transmission of signals approaching the positive supply. Such a function would otherwise require use of a p-channel MOS device in parallel with the n-channel device, with a complementary gating signal. Other possible applications for the drive circuit of the present invention include use in: (1) pad circuits which must interface with higher voltage technologies, (2) FPGA, (3) fuse circuits, (4) DRAM, (5) EEPROM, and (6) flash memory.
The attainment of the foregoing and related advantages and features of the invention should be more readily apparent to those skilled in the art, after review of the following more detailed description of the invention taken together with the drawings.